Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
High Speed Digital Blocks
Current-Mode-Logic (CML) Latch | EveryNano Counts
adding reset function to D Flip FLOP | Forum for Electronics
KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
DFF-based CMOS clock divider. | Download Scientific Diagram
ECEN620: Network Theory Broadband Circuit Design Fall 2022
An improved current mode logic latch for high‐speed applications
ECEN620: Network Theory Broadband Circuit Design Fall 2022
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Current-Mode-Logic (CML) Latch | EveryNano Counts
MIPI homepage CMOS prescaler basics
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
CML based DFF combined with NAND function used in 4/5 prescaler block | Download Scientific Diagram
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider: Ravindran Mohanavelu and Payam Heydari | PDF
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
Current Mode Logic Divider
Figure 2 from New CML latch structure for high speed prescaler design | Semantic Scholar
